1. Field of the Invention
Embodiments of the invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to NAND-type nonvolatile semiconductor memory devices including dummy cells.
A claim of priority is made to Korean Patent Application No. 2006-64525 filed on Jul. 10, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
A NAND-type nonvolatile memory device comprises a memory cell array comprising a plurality of nonvolatile memory cells arranged in a plurality of strings. The strings in a NAND-type nonvolatile memory device are commonly referred to as NAND cell stings, or NAND strings for short. In a typical NAND string, a plurality of nonvolatile memory cells are connected to each other in series between a common source line and a bit line. The memory cells in each NAND string are connected to the bit line through a string select transistor and to the common select line CSL through a ground select transistor.
In order to increase the integration density of NAND-type nonvolatile memory devices, researchers continue to develop new ways of shrinking the size and separating distance of elements in the devices. In addition, another way to increase the integration density of NAND-type nonvolatile memory devices is by including more memory cell transistors in each NAND string. By increasing the number of memory cell transistors per string, the relative proportion of chip area occupied by control elements such as the ground select transistor and the string select transistor, as opposed to the proportion occupied by memory elements, tends to decrease. As a result, adding more memory cells per NAND string tends to increase the data storage capacity per chip area of a NAND-type nonvolatile memory device.
FIG. 1 shows a NAND-type nonvolatile memory device comprising several NAND cell strings each comprising 32 memory cell transistors. FIG. 2, on the other hand, shows a NAND-type nonvolatile memory device comprising several NAND cell strings each comprising 64 memory cell transistors.
Referring to FIG. 1, the NAND-type nonvolatile memory device comprises a plurality of cell arrays, each comprising a memory field MEM and a selection field SELi, where “i” is an integer equal to 1, 2, or 3. The cell arrays are arranged in a mirror pattern where each pair of adjacent cell arrays shares a selection field SELi.
Each memory field MEM in FIG. 1 comprises a plurality of NAND strings. Each of the NAND strings comprises 32 memory cell transistors Tc connected in series between a string select transistor Ts in one of selection fields SEL1 or SEL3, and a ground select transistor in selection field SEL2. The NAND strings are arranged in columns, and respective memory cell transistors Tc within the NAND strings align to form rows, where each row of memory cell transistors Tc is commonly connected to one of a plurality of word lines WL00 through WL31. A row of memory cells transistors Tc commonly connected to a word line will be referred to hereafter as a “page” of memory cells. Often, a NAND-type memory array will be programmed by a unit of an entire page at a time.
Each of the NAND strings in FIG. 1 is connected to a corresponding one of a plurality of bitlines BL00 through BLn via its string select transistor Ts. In addition, each of the NAND strings is connected to a common select line CSL via its ground select transistor Tg.
The NAND-type nonvolatile memory device illustrated in FIG. 2 is similar to the NAND-type nonvolatile memory device illustrated in FIG. 1, except that in FIG. 2, each NAND string includes 64 memory cells connected in series between a ground select transistor Tg in selection field SEL1 and a string select transistor Ts in selection field SEL2.
Because the NAND-type semiconductor memory device of FIG. 2 dedicates a relatively smaller area to selection fields than the NAND-type semiconductor memory device of FIG. 1, the NAND-type semiconductor memory device of FIG. 2 can provide a higher amount of data storage per chip area than the NAND-type semiconductor memory device of FIG. 1.
Unfortunately, however, most NAND-type nonvolatile memory devices perform erase operations in units of entire arrays, also called “blocks”. In other words, all of the NAND strings located in the same memory field MEM are usually erased at the same time. As a result, increasing the number of memory cells per NAND string may have the undesirable side effect of creating a more cumbersome, less flexible file system. As a result, even though such devices may be able to achieve a higher integration density, this benefit may be offset by a decreased efficiency due to the coarser granularity of erase operations.